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| Features * * * * * * * * * One 128 x 8 (1K bit) Configuration Zone Eight 256 x 8 (16K bits) User Zones Low Voltage Operation: 2.7V to 5.5V Two-wire Serial Interface 16-byte Page Write Mode Self Timed Write Cycle (10 ms max) ISO 7816-3 Synchronous Protocol Answer-to-Reset Register High Security Memory Including Anti-wire Tapping - 64-bit Authentication Protocol* - Authentication Attempts Counter - Eight Sets of Two 24-bit Passwords - Specific Passwords for Read and Write - Sixteen Password Attempts Counters - Selectable Access Rights by Zone * ISO Compliant Packaging * High Reliability - Endurance: 100,000 Cycles - Data Retention: 100 Years - ESD Protection: 4,000V min * Low-Power CMOS 8 x 256 x 8 Secure Memory with Authentication AT88SC1608 Description The AT88SC1608 provides 17,408 bits of serial EEPROM memory organized as one configuration zone of 128 bytes and eight user zones of 256 bytes each. This device is optimized as a "secure memory" for the smart card market, secure identification for electronic data transfer or for components in a system, without the requirement of an internal microprocessor. The embedded authentication protocol allows the memory and the host to authenticate each other. When this device is used with a host which incorporates a microcontroller, e.g., AT89C51, AT89C2051, AT90S1200, the system provides an "anti-wire tapping" configuration. The device and the host exchange "challenges" issued from a random generator and verify their values through a specific cryptographic function included in each part. When both agree on the same result, the access to the memory is permitted. Security Methodology Rev. 0971E-11/99 *Under exclusive patent license from ELVA 1 Memory Access Depending on the device configuration, the host might carry out the authentication protocol, and/or present different passwords for each operation: read or write. Each user zone may be configured for free access for read and write, or for password restricted access. To insure security between the different user zones (multi-application card), each zone can use a different set of passwords. An A tt em p ts Co u nt er s p ec i f ic t o e ac h pa s s wo r d a n d authentication provides protection against "systematic attacks". When the memory is unlocked, the two-wire serial protocol is effective, using SDA and SCL. The memory includes a specific register providing a 32-bit data stream conforming to the ISO 7816-3 synchronous Answer-toReset. Block Diagram VCC GND Power Mgt. Authentication Unit Random Generator SCL SDA ISO Interface Data Transfer Password Verification EEPROM RST Answer-to-Reset Pin Descriptions Supply Voltage (VCC) The VCC input is a 2.7V to 5.5V positive voltage, supplied by the host. number of other open drain or open collector devices. Atmel recommends a 4.7 K pull up resistor connected between VCC and SDA. Serial Clock (SCL) The SCL input is used to positive edge clock data into the device and negative edge clock data out of the device. Reset (RST) When the RST input is pulsed high, the device will output the data programmed into the 32-bit Answer-to-Reset register. All password and authentication access will be reset. Following a reset, device authentication and password verification sequences must be presented to reestablish user access. Serial Data (SDA) The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven, and may be wire-ORed with any 2 AT88SC1608 AT88SC1608 Memory Mapping The first 16K bit of the memory are divided in eight user zones of 256 bytes each: Zone $0 $1 $2 $3 $4 $5 $6 $7 $000 256 bytes User 0 $0F8 User 1 User 6 $100 $6F8 $700 256 bytes User 7 $7F8 Note: $ denotes hexadecimal value - The last 1K bit of the memory is a configuration zone with specific system data, access rights and read/write commands; itself divided in six subzones: Configuration Fabrication Fab Code AR0 Access Reserved for Future Use AAC Authentication Cryptogram (Ci) Secret Test PAC PAC PAC Passwords PAC PAC PAC PAC PAC Notes: 1. 2. Write 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Secure Code / Write 7 Secret Seed (Gc) Reserved for Memory Test PAC PAC PAC PAC PAC PAC PAC PAC 3. Read 0 Read 1 Read 2 Read 3 Read 4 Read 5 Read 6 Read 7 $28 $30 $38 $40 $48 $50 $58 $60 $68 $70 $78 Identification Number (Nc) $18 $20 AR1 Reserved AR2 AR3 AR4 Card Manufacturer Code AR5 AR6 AR7 $08 $10 $0 $1 $2 $3 $4 $5 $6 $7 $00 Answer-to-Reset Lot History Code AAC: Authentication Attempts Counter. PAC: Password Attempts Counter. AR0-7: Access Register for User Zone 0 to 7. 3 Fuses * FAB, CMA and PER are nonvolatile fuses blown at the end of each card life step. Once blown, these EEPROM fuses can not be reset. * The FAB fuse is blown by Atmel prior to shipping wafers to the card manufacturer. * The CMA fuse is blown by the card manufacturer prior to shipping cards to the issuer. * The PER fuse is blown by the issuer prior to shipping cards to the end user. The Fuses are read and written in the configuration zone using the address $80: Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 PER Bit 1 CMA Bit 0 FAB $80 When the fuses are all 1's, read and write are allowed in the entire memory. Before blowing the FAB fuse, Atmel writes the entire memory to "1", except the fabrication subzone and the secure code. In the following table, CMC is the Card Manufacturer Code, and AR means the access rights are defined by the access registers. Configuration Fabrication (Except CMC) Fabrication (Only CMC) Access Write Read Authentication Write Read Secret Write Read Test Write Read Passwords Write Read PAC Write Read User Zones Write AR AR AR Secure Code AR Secure Code AR Write PW AR Secure Code Free Secure Code Free Write PW Free Free Secure Code Free Secure Code Free Write PW Secure Code Free Secure Code Free Forbidden Free Secure Code Secure Code Secure Code Secure Code Forbidden Forbidden Secure Code Free Secure Code Free Forbidden Free Access Read Write Read Write Read FAB = 0 Free Forbidden Free Secure Code Free CMA = 0 Free Forbidden Free Forbidden Free PER = 0 Free Forbidden Free Forbidden Free 4 AT88SC1608 AT88SC1608 Configuration Zone Answer-to-Reset 32-bit register defined by Atmel. RPE - Read Password Enable If enabled (RPE = "0"), the user is required to verify either the Read Password or Write Password to allow read operations in the user zone. Read operations initiated without a verified password will return the status of the fuse bits ($00). Verification of the Write password will always allow read access to the zone. RPE = "0" and WPE = "1" is allowed, but is not recommended. ATE - Authentication Enable If enabled (ATE = "0"), a valid authentication sequence must be completed before access is allowed to the user zone. If disabled (ATE = "1"), authentication is not required for access. PW2, PW1, PW0 - Password Set Select These three bits define which of the eight password sets must be presented to allow access to the user zone. Each access register may point to a unique password set, or access registers for multiple zones may point to the same password set. In this case, verification of a single password will open several zones, combining the zones into a single larger zone. MDF - Modify Forbidden If enabled (MDF = "0"), no write access is allowed in the zone at any time. PGO - Program Only If enabled (PGO = "0"), data within the zone may be changed from "1" to "0", but never from "0" to "1". Lot History Code 32-bit register defined by Atmel. Fab Code 16-bit register defined by Atmel. Card Manufacturer Code 32-bit register defined by the card manufacturer. Access Registers Eight 8-bit access registers defined by the issuer. (Enable if "0"). The Access register for each user zone will specify the privileges and requirements for access to that zone. Bit 7 WPE Bit 6 RPE Bit 5 ATE Bit 4 PW2 Bit 3 PW1 Bit 2 PW0 Bit 1 MDF Bit 0 PGO WPE - Write Password Enable If enabled (WPE = "0"), the user is required to verify the Write Password to allow write operations in the user zone. If disabled (WPE = "1"), all write operations are allowed within the zone. Verification of the Write password also allows the Read and Write passwords to be changed. During personalization (PER = "1") the WPE bit is forced active, even if set to "1". This forces the issuer to verify the Write Password, in order to write data to the user zone. This allows the security code (Write 7 password) to lock write functions during transportation. 5 Configuration Zone (continued) Identification Number (Nc) An identification number with up to 56-bits is defined by the issuer and should be unique for each card. Security Operations Password Verification Compare the operation password presented with the stored one, and write a new bit in the corresponding attempts counter for each wrong attempt. A valid attempt before the limit erases the attempts counter, and allows the operation to be carried out as long as the chip is powered. Only one password is allowed to be valid at any time. When a new password is presented, access privileges defined by the previous password become invalid. If the trials limit has been reached (i.e. the 8 bits of the attempts counter have been written), the password verification process will not be taken into account. Authentication Protocol The access to a user zone may be protected by an authentication protocol in addition to password dependent rights. The authentication success is memorized and active, as long as the chip is powered, unless a new authentication is initialized or RST becomes active. If the new authentication request is not validated, the card loses its previous authentication and it should be presented again. Only the last request is memorized. Note: The password and authentication may be presented at any time and in any order. Cryptogram (Ci) The 64-bit cryptogram is generated by the internal random generator and modified after each successful verification of the cryptogram by the chip, on host request. The initial value, defined by the issuer, is diversified as a function of the identification number. Secret Seed (Gc) The 64-bit secret seed, defined by the issuer, is diversified as a function of the identification number. Memory Test Zone 64-bit free access zone for memory test. Password Sets Eight sets of two 24-bit passwords for read and write operations, defined by the issuer. The Write Password allows the user to modify the Read and Write passwords of the same set. By default, the eighth set of passwords (Write 7 / Read 7) is active for all user zones. Secure Code 24-bit password, defined by Atmel, is different for each card manufacturer. The Write Password 7 is used as the Secure Code until the personalization is over (PER = 0). User Zones These zones are dedicated to user data. The access rights of each zone are programmable separately via the access registers. If several zones share the same password set, the set will be entered only once (after the part is powered up). Therefore, several zones can be combined into one larger zone. The user zone address should be changed each time a new zone is being reached. Attempts Counters (PAC and AAC) Sixteen 8-bit Attempts Counters, one for each password (PAC), and one other 8-bit Attempts Counter for the authentication protocol (AAC). The Attempts Counters limit the number of consecutive incorrect code presentations allowed (currently 8). 6 AT88SC1608 AT88SC1608 AT88SC1608 Command Definitions and Protocols The ISO compliant interface is based on the popular two-wire serial interface. Note that the MOST significant bit is transmitted first. Command Chip Select b7 1 1 1 1 1 1 1 1 b6 0 0 0 0 0 0 0 0 b5 1 1 1 1 1 1 1 1 b4 1 1 1 1 1 1 1 1 b3 0 0 0 0 0 0 0 0 Instruction b2 0 0 1 1 0 0 1 1 b1 0 0 0 0 1 1 1 1 b0 0 1 0 1 0 1 0 1 Write User Zone Read User Zone Write Configuration Zone Read Configuration Zone Set User Zone Address Verify Password Initialize Authentication Verify Authentication $B0 $B1 $B4 $B5 $B2 $B3 $B6 $B7 Description Code HEX Set User Zone Address Command Note: * = Don't care bit At power on, no access to the user zones is allowed until the Set User Zone Address command occurs. This command sets the three most significant bits of the byte address, corresponding to the user zone address. This address stays valid until the host sends a new one, and as long as the chip is powered. 7 Read Zone Command Notes: 1. z = 0 : Read user zone 2. z = 1 : Read configuration zone The data byte address is internally incremented following the transmission of each data byte. As long as the AT88SC1608 receives an acknowledge from the host, it will continue to increment the data byte address and serially clock out sequential data bytes. During a read operation, the address will "roll over" from the last byte of the current zone, to the first byte of the same zone. If the host is not allowed to read at the specified address, the device will transmit the data byte with all bits equal to "0". Write Zone Command Notes: 1. z = 0 : Write user zone 2. z = 1 : Write configuration zone The lower four bits of the data byte address are internally incremented following the receipt of each data byte. The higher data byte address bits are not incremented, retaining the 16-byte write-page address. Each data byte within a page must only be loaded once. Once a stop condition is issued to indicate the end of the host's write command, the device initiates the internally timed nonvolatile write cycle. An ACK polling sequence can be initiated immediately. After a write command, if the host is not allowed to write to s ome addr ess locations, a nonvolatile write cycle will still be initiated. However, the device will only modify data at the allowed addresses. 8 AT88SC1608 AT88SC1608 Read Fuses Command Notes: 1. Fx = 1 : fuse is not blown 2. Fx = 0 : fuse is blown The Read Fuses operation is always allowed. The device only transmits one data byte and waits for a new command. Write Fuses Command The Write Fuses operation is only allowed under secure code control and no data byte is transmitted by the host. The fuses are blown sequentially: CMA is blown if FAB is equal to "0", and PER is blown if CMA is equal to "0". If the fuses are all 0's, the operation is canceled and the device waits for a new command. Once a stop condition is issued to indicate the end of the host's write operation, the device initiates the internal nonvolatile write cycle. An ACK polling sequence can be initiated immediately. Once blown, these fuses can not be reset. 9 Answer-to-Reset If RST is high during SCL clock pulse, the reset operation occurs according to the ISO 7816-3 synchronous Answerto-Reset. The 4 bytes of the Answer-to-Reset register are transmitted LEAST significant bit (LSB) first, on the 32 The values programmed by Atmel are: clock pulses provided on SCL. Following a RST assertion, all password and authentication access privileges are reset. Verify Password Command Notes: 1. 2. Pw: Password, 3 bytes. The four bits "rppp" indicate the password to compare: r = 0: Write password, r = 1: Read password, ppp: Password set number. (rppp = 0111 for the secure code). Once the sequence is completed and a stop condition is issued, there is a nonvolatile write cycle to update the associated attempts counter. In order to know whether or not the inserted password was correct, the device requires the host to perform an ACK polling sequence with the specific device address of $B5. When the write cycle has completed, the ACK polling command ($B5, Read Configuration Zone) will return a valid ACK. This command should be followed by the byte address of the respective Password Attempts Counter. If the password presented is valid, the Password Attempts Counter will be set to $FF. If the password was not valid, the Password Attempts Counter will have one additional bit written to "0". 10 AT88SC1608 AT88SC1608 Initialize Authentication Command Note: Q0: Host random number, 8 bytes. The initialize authentication command sets up the random generator with the cryptogram (Ci), the secret seed (Gc) and the host random number (Q0). Once the sequence is completed and a stop condition is issued, there is a nonvolatile write cycle to write a new bit of the 8 bit authentication attempts counter to "0". In order to complete the authentication protocol, the device requires the host to perform an ACK polling sequence with the specific device address of $B7, corresponding to the Verify Authentication command. Verify Authentication Command Note: Q1: Host challenge, 8 bytes. If Q1 is equal to Ci+1, then the device writes Ci+2 in memory in place of Ci; this must be preceded by the Initialize Authentication command. Once the sequence is completed and a stop condition is issued, there is a nonvolatile write cycle to update the associated Attempts Counter. In order to know whether or not the authentication was correct, the device requires the host to perform an ACK polling sequence with the specific device address of $B5 to read the Authentication Attempts Counter in the configuration zone. A valid Authentication will result in the AAC cleared to $FF. An invalid Authentication attempt will initiate a nonvolatile write cycle, but no clear operation will be performed on the AAC. 11 Packaging Name VCC GND SCL SDA RST Description Supply Voltage Ground Serial Clock Input Serial Data Input/Output Reset Input ISO Module Contact C1 C5 C3 C7 C2 Standard Package Pin 8 1 6 3 7 Card Module Contact VCC = C1 RST = C2 SCL = C3 NC = C4 C5 = GND C6 = NC C7 = SDA C8 = NC 8-pin SOIC, PDIP, EIAJ or LAP GND NC SDA NC 1 2 3 4 8 7 6 5 VCC RST SCL NC Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the device in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data are serially transmitted to and from the device in 8-bit words. The device sends a zero to acknowledge that it has received each byte. This happens during the ninth clock cycle. During Read operations, the host must pull the SDA line low during the ninth clock cycle to acknowledge that it has received the data byte. Failure to transmit this ACK bit will terminate the Read operation. STANDBY MODE: The AT88SC1608 features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the device inputs are disabled, acknowledge polling can be initiated. This involves sending a s t a r t c o n d i t i o n fo l l o w e d b y t h e d e v i c e a d d r e s s representative of the operation desired. Only if the internal write cycle has completed will the device respond with a zero, allowing the sequence to continue. 12 AT88SC1608 AT88SC1608 Start and Stop Definition Note: The SCL input should be LOW when the device is idle. Therefore, SCL is LOW before a start condition and after a stop condition. Data Validity SDA SCL DATA STABLE DATA CHANGE DATA STABLE Output Acknowledge 13 Absolute Maximum Ratings* *NOTICE: Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground ............................. -0.7V to VCC + 0.7V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics DC Characteristics Applicable over recommended operating range from: VCC = +2.7V to 5.5V, TAC = 0C to +70C. (unless otherwise noted). Symbol VCC(1) ICC ICC ISB1 ISB2 ILI ILO VIL VIH VOL2 Notes: (1) Parameter Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level (2) Test Condition Min 2.7 Typ Max 5.5 5.0 5.0 1.0 5.0 1.0 1.0 Units V mA mA A A A A V V V READ at 1MHz WRITE at 1MHz VIN = VCC or GND VIN = VCC or GND VIN = VCC or GND VOUT = VCC or GND -0.3 VCC x 0.7 IOL = 2.1 mA VCC x 0.3 VCC + 0.5 0.4 Input High Level (2) Output Low Level VCC = 2.7V 1. This parameter is preliminary and Atmel may change the specifications upon further characterization. 2. VIL min and VIH max are reference only and are not tested. Power Management If VCC falls below 1.9V, the chip stops working until it rises above 2.7V. 14 AT88SC1608 AT88SC1608 AC Characteristics Applicable over recommended operating range from TA = 0C to +70C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). 5.0-volt Symbol fSCL tLOW tHIGH tAA tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR tRST tSU.RST tHD.RST Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time (1) Min Max 1.0 Units MHz ns ns 400 400 35 200 200 10 100 100 30 200 20 10 600 50 50 ns ns ns ns ns ns ns ns ns ms ns ns ns Inputs Fall Time (1) Stop Set-up Time Data Out Hold Time Write Cycle Time Reset Width High Reset Set-up Time Reset Hold Time This parameter is characterized and is not 100% tested. Pin Capacitance Applicable over recommended operating conditions TA = 25C, f = 1.0 MHz, VCC = +2.7V. Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (RST, SCL) This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V 15 Bus Timing SCL: Serial Clock SDA: Serial Data I/O Synchronous Answer-to-Reset Timing Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O SCL SDA 8th BIT WORD n ACK t WR STOP CONDITION START CONDITION Note: The write cycle Time tWR is the time from valid stop condition of a write sequence to the end of the internal clear/write cycle. 16 AT88SC1608 AT88SC1608 Ordering Information Ordering Code(1) AT88SC1608 - 09AT - xx - 2.7 AT88SC1608 - 09BT - xx - 2.7 AT88SC1608 - 09CT - xx - 2.7 AT88SC1608 - 09DT - xx - 2.7 AT88SC1608 - 09LT - xx - 2.7 AT88SC1608 - 10WC - xx - 2.7 AT88SC1608 -10PC - xx - 2.7 AT88SC1608 - 10CC - xx - 2.7 AT88SC1608 - 09AT - xx AT88SC1608 - 09BT - xx AT88SC1608 - 09CT - xx AT88SC1608 - 09DT - xx AT88SC1608 - 09LT - xx AT88SC1608 - 10WC - xx AT88SC1608 -10PC - xx AT88SC1608 - 10CC - xx Package(2) M2 - A Module M2 - B Module M4 - C Module M4 - D Module M2 - L Module 8S2 8P3 8C M2 - A Module M2 - B Module M4 - C Module M4 - D Module M2 - L Module 8S2 8P3 8C Voltage Range Temperature Range 2.7V to 3.3V Commercial 0C to 70C 4.5V to 5.5V Commercial 0C to 70C Package Type(2) M2 - A Module M2 - B Module M4 - C Module M4 - D Module M2 - L Module 8S2 8P3 8C Notes: M2 ISO 7816 Smart Card Module M2 ISO 7816 Smart Card Module with Atmel Logo M4 ISO 7816 Smart Card Module M4 ISO 7816 Smart Card Module with Atmel Logo M2 ISO 7816 Smart Card Module 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.230" Wide, Leadless Array Package (LAP) 1. "xx" must be replaced by a security code. Contact an Atmel Sales Office for the security code. 2. Formal drawings may be obtained from an Atmel Sales Office. 17 Smart Card Modules M2 - A Module - Ordering Code: 09AT M4 - D Module - Ordering Code: 09DT Module Size: M2 Dimension(1): 12.6 x 11.4 mm Glob Top: Black, Square: 8.6 x 8.6 mm Thickness: 0.58 mm max. Pitch: 14.25 mm M2 - B Module - Ordering Code: 09BT Module Size: M4 Dimension(1): 12.6 x 12.6 mm Glob Top: Black, Square: 8.6 x 8.6 mm Thickness: 0.58 mm max. Pitch: 14.25 mm M2 - L Module - Ordering Code: 09LT Module Size: M2 Dimension(1): 12.6 x 11.4 mm Glob Top: Black, Square: 8.6 x 8.6 mm Thickness: 0.58 mm max. Pitch: 14.25 mm M4 - C Module - Ordering Code: 09CT Module Size: M2 Dimension(1): 12.6 x 11.4 mm Glob Top: Black, Square: 8.6 x 8.6 mm max. Thickness: 0.58 mm max. Pitch: 14.25 mm Note: 1. The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e. a punched M2 module will yield 13.0 x 11.8 mm). Module Size: M4 Dimension(1): 12.6 x 12.6 mm Glob Top: Black, Square: 8.6 x 8.6 mm Thickness: 0.58 mm Pitch: 14.25 mm 18 AT88SC1608 AT88SC1608 Packaging Information 8S1, 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) .020 (.508) .013 (.330) 8S2, 8-lead, 0.210" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters) .020 (.508) .012 (.305) PIN 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) PIN 1 .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) .050 (1.27) BSC .050 (1.27) BSC .196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35) .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .010 (.254) .004 (.102) 0 REF 8 .050 (1.27) .016 (.406) .010 (.254) .007 (.203) 0 REF 8 .013 (.330) .004 (.102) .010 (.254) .007 (.178) .035 (.889) .020 (.508) 8P3, 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) 8C, 8-lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) SIDE VIEW .400 (10.16) .355 (9.02) PIN 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690) TOP VIEW 5.03 (0.198) 4.83 (0.190) .300 (7.62) REF .210 (5.33) MAX SEATING PLANE .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .100 (2.54) BSC 6.09 (0.240) 5.89 (0.232) BOTTOM VIEW 1.14 (0.045) 0.94 (0.037) 0.38 (0.015) 0.30 (0.012) 1.19 (0.047) 1.09 (0.043) .015 (.380) MIN .022 (.559) .014 (.356) 1.32 (0.052) 1.22 (0.048) 8 3.86 (0.152) 3.76 (0.148) 7 6 5 0.60 (0.024) 0.50 (0.020) 1 2 3 4 0.89 (0.035) 0.79 (0.031) 0.61 (0.024) 0.51 (0.020) .325 (8.26) .300 (7.62) .012 (.305) .008 (.203) 0 REF 15 .430 (10.9) MAX 19 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper. 0971E-11/99/xM Terms and product names in this document may be trademarks of others. |
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